| 发明名称 |
Distributed FIFO in synchronous memory |
| 摘要 |
A synchronous memory device includes a distributed FIFO buffer in a read path. Buffer stages of the FIFO are located at remote ends of an internal data bus. The time needed for loading the first FIFO stage is reduced and allows shorter clock cycle times for some memory read operations.
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| 申请公布号 |
US6678201(B2) |
申请公布日期 |
2004.01.13 |
| 申请号 |
US20020118281 |
申请日期 |
2002.04.08 |
| 申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
ROOHPARVAR FRANKIE FARIBORZ;NOBUNAGA DEAN |
| 分类号 |
G11C7/10;G11C19/00;G11C19/18;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
| 代理机构 |
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