发明名称 |
INPUT OUTPUT BUFFER, INPUT BUFFER, AND OUTPUT BUFFER |
摘要 |
PROBLEM TO BE SOLVED: To provide an input output buffer capable of protecting its circuitry against a voltage signal received externally independently of application / non application of operating power. SOLUTION: The input output buffer is provided with a power supply generating circuit 16 that converts the voltage signal EB externally received into a proper level corresponding to a high level power supply VDE to generate a reference power supply VDO. The power supply generating circuit 16 is provided with diode-connected transistors Pt 11 to Pt 15, and the back-gates of the transistors Pt 11 to Pt 15 are connected to nodes having levels other than the levels of the high level power supply VDE and a low level power supply VSS. Thus, it is prevented that a high voltage is applied between the gate and the back-gate of the transistors Pt 11 to Pt 15 at the application of the external voltage signal EB to the input and output buffer independently of application / non application of the high level power supply VDE. COPYRIGHT: (C)2004,JPO
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申请公布号 |
JP2004007212(A) |
申请公布日期 |
2004.01.08 |
申请号 |
JP20020159696 |
申请日期 |
2002.05.31 |
申请人 |
FUJITSU LTD;FUJITSU VLSI LTD |
发明人 |
YAJIMA HIDEAKI |
分类号 |
H03F1/52;H03F1/56;H03K19/003;H03K19/0175;(IPC1-7):H03K19/017 |
主分类号 |
H03F1/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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