发明名称 |
Charge pump circuit for a PLL |
摘要 |
A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.
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申请公布号 |
US2004004500(A1) |
申请公布日期 |
2004.01.08 |
申请号 |
US20030438178 |
申请日期 |
2003.05.13 |
申请人 |
BERKANA WIRELESS, INC. |
发明人 |
BYUN SANG JIN;KIM BEOMSUP;PARK CHAN-HONG |
分类号 |
H03L7/089;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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