| 摘要 |
A power integrity analysis integration tool for analyzing the power integrity of a semiconductor layout previously designed using a separate design tool. The power integrity analysis integration tool includes a graphic user interface that is configured to extract layout data from the design tool and perform a transistor-level analysis of the power integrity of the semiconductor layout. A method of designing a semiconductor layout and performing a transistor-level analysis of the power integrity of the semiconductor layout includes, first, using a design tool to design the semiconductor layout, and then using the power integrity analysis integration tool to extract layout data from the design tool and perform a transistor-level analysis of the power integrity of the semiconductor layout.
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