发明名称 Multi-instruction stream processor
摘要 The present invention discloses apparatus for, and a method of, rendering image data prior to outputting of the resulting image. A graphics co-processor (224) is utilized together with a host CPU (202), the former having a plurality of data calculation streams (241, 242, 243) arranged in parallel fashion. Only one of the data calculation streams (241, 242, 243) is operated at any one time. Preferably at least one (242) of the data calculation streams is able to be reconfigured.
申请公布号 US6674536(B2) 申请公布日期 2004.01.06
申请号 US19980025768 申请日期 1998.02.18
申请人 CANON KABUSHIKI KAISHA 发明人 LONG TIMOTHY MERRICK;GIBSON IAN;AMIES CHRISTOPHER
分类号 G06F9/38;G06T1/20;G06T15/00;(IPC1-7):G06F3/12;G06F13/00 主分类号 G06F9/38
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