| 发明名称 |
Distributed test architecture for multiport RAMs or other circuitry |
| 摘要 |
An apparatus comprising a first circuit and a second circuit. The first circuit generally comprises a first built in self test (BIST) circuit configured to test the first circuit. The second circuit generally comprises a second BIST circuit configured to test the second circuit. The second circuit may not be adjacent to the first circuit.
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| 申请公布号 |
US6675336(B1) |
申请公布日期 |
2004.01.06 |
| 申请号 |
US20000592700 |
申请日期 |
2000.06.13 |
| 申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
THAKUR SANGEETA;HAMADEH EMAD;NARAYANA PIDUGU L. |
| 分类号 |
G01R31/3185;G11C29/12;(IPC1-7):G01R31/28;G11C29/00 |
主分类号 |
G01R31/3185 |
| 代理机构 |
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