| 发明名称 |
Integrated circuit design and manufacture utilizing layers having a predetermined layout |
| 摘要 |
Systems and methods are provided that improve the efficiency of integrated circuit layout. The systems and methods provided herein also reduce the mask cost for ASIC and integrated circuit design.
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| 申请公布号 |
US2004003363(A1) |
申请公布日期 |
2004.01.01 |
| 申请号 |
US20020184562 |
申请日期 |
2002.06.27 |
| 申请人 |
ODILAVADZE NICKOLAI;BIRIOUKOV GEORGIY |
发明人 |
ODILAVADZE NICKOLAI;BIRIOUKOV GEORGIY |
| 分类号 |
G06F17/50;H01L27/02;H01L27/118;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
| 代理机构 |
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