发明名称 |
Memory having a precharge circuit and method therefor |
摘要 |
A magnetoresistive random access memory (MRAM) has separate read and write paths. Switchable current mirrors, each having multiple series-connected stages, receive a common reference current. A timing circuit provides control signals to word and bit decoders and to the switchable current mirrors to selectively complete current paths through a predetermined write word line and a predetermined write bit line. Bit lines are connected together at a common end, and word lines are connected together at a common end. By precharging a common rail having multiple write bit lines connected together, the write noise immunity is improved and current spikes are minimized. Groups of bit lines may be connected via a metal option to adjust a transition time of a programming current.
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申请公布号 |
US2004001351(A1) |
申请公布日期 |
2004.01.01 |
申请号 |
US20020185488 |
申请日期 |
2002.06.28 |
申请人 |
SUBRAMANIAN CHITRA K.;ANDRE THOMAS W.;NAHAS JOSEPH J. |
发明人 |
SUBRAMANIAN CHITRA K.;ANDRE THOMAS W.;NAHAS JOSEPH J. |
分类号 |
G11C11/16;(IPC1-7):G11C11/00 |
主分类号 |
G11C11/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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