System and method for statistical modeling and statistical timing analysis of integrated circuits

摘要

A comprehensive methodology for statistical modeling and timing of integrated circuits and integrated circuit macros is disclosed with a means for efficiently computing the sensitivities of coefficients of gate delay models to sources of variation. These sensitivities are used to determine the probability distribution of the delay and slew of each gate and wire, as well as the correlations between these delays and slews. Finally, these timing models are used in an inventive statistical static timing analysis method to predict the statistical performance of an integrated circuit or integrated circuit macro.