| 摘要 |
PURPOSE: A device and method for an FPGA(Field Programmable Gate Array) interface using a unibus is provided to verify a CPU board using many field programmable gate arrays when the CPU board is designed. CONSTITUTION: Many FPGAs(10,20,30) are connected to a global bus and execute a communication through the global bus with an exterior. Each FPGA(10,20,30) includes an FPGA interface module and executes a communication through the FPGA interface module among the global bus, a master processor, and a slave processor. The FPGA(10) includes master processors(11,12), slave processors(13,14), an arbiter(15), a decoder(16), and an FPGA interface module(17). The FPGA interface module(17) includes a master inside(MI), a master outside(MO), a slave inside(SI), and a slave outside(SO). The FPGA(20) includes master processors(21,22), slave processors(23,24), an arbiter(25), a decoder(26), and an FPGA interface module(27). The FPGA interface module(27) includes a master inside(MI), a master outside(MO), a slave inside(SI), and a slave outside(SO). The FPGA(30) includes master processors(31,32), slave processors(33,34), an arbiter(35), a decoder(36), and an FPGA interface module(37). The FPGA interface module(37) includes a master inside(MI), a master outside(MO), a slave inside(SI), and a slave outside(SO). Each master processor is connected to the slave inside(SI), respectively, and the slave inside(SI) is connected to the master outside(MO). The slave outside(SO) connected to the global bus is connected to the master inside(MI). Each master inside(MI) is connected to the slave processor, respectively. One out of the FPGA(10,20,30) includes a global arbiter(GA) and a global decoder(GD).
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