发明名称 METHOD FOR FORMING DUAL DAMASCENE INTERCONNECTION OF SEMICONDUCTOR DEVICE
摘要 PURPOSE: A method for forming a dual damascene interconnection of a semiconductor device is provided to be capable of preventing the etching phenomenon of a passivation layer when carrying out a rework process, by carrying out a trench etching process after forming a capping layer at the upper portion of the passivation layer. CONSTITUTION: The first etch stopper(310), the first interlayer dielectric(320), and the second interlayer dielectric(340) are sequentially formed at the upper portion of a semiconductor substrate(300), wherein the semiconductor substrate has a damascene interconnection(305). A via hole is formed by selectively etching the resultant structure. Then, a passivation layer(370) is formed at the via hole. After forming a capping layer(380) at the upper portion of the passivation layer, a trench is formed by selectively etching the capping layer, the passivation layer, and the second interlayer dielectric. Then, an interconnection is formed at the dual damascene pattern made of the via hole and the trench.
申请公布号 KR20030096730(A) 申请公布日期 2003.12.31
申请号 KR20020033736 申请日期 2002.06.17
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 JANG, HO SEON;KIM, IL GU
分类号 H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/768
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