| 摘要 |
A delta-sigma modulator that provides improved SNR performance in applications such as low-power mobile wireless communications and high frequency radar applications is disclosed. Multiple comparators 10, each comprising a sequence of three latches 20, 22, 24, connect the modulator's input filter circuit 12 to the modulator's output interfaces 14, providing quantization of the integrated, filtered signal provided by the filter circuit 12. A clock signal having a cycle period Tc enables a first latch 20 connected to the signal input of each comparator 10 to provide a digital signal to the signal input of a second latch 22. The second latch 22 supplies a digital signal to a third latch 24 in the sequence, in response to the signal received from the first latch 20, by a lagged clock signal derived from the given clock signal Tc by providing a first lag time TL where Tc/2>=TL>0. A third latch in the sequence is enabled by a clock signal having a second lag time TS=Tc/2+TE, and the delay TE<<Tc/2. When TL=Tc/2 the inverted clock signal supplied to the second latch is delayed and supplied to the third latch. When TL=TE the delayed clock signal supplied to the second latch is inverted and supplied to the third latch.
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