发明名称 |
Method and circuit for increasing the memory access speed of an enhanced synchronous SDRAM |
摘要 |
An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective set of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a "bank activate" command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a "read" command to the SDRAM. Column decoders decode a column address in response to a "read" command and for reading data from the cache in accordance with the decoded column address.
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申请公布号 |
US2003236958(A1) |
申请公布日期 |
2003.12.25 |
申请号 |
US20020178072 |
申请日期 |
2002.06.20 |
申请人 |
MOBLEY KENNETH J.;PETERS MICHAEL T.;SCHUETTE MICHAEL |
发明人 |
MOBLEY KENNETH J.;PETERS MICHAEL T.;SCHUETTE MICHAEL |
分类号 |
G06F12/00;G06F12/08;G11C11/4097;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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