| 摘要 |
A pulse generation circuit generates an output pulse that is set to its activated level in response to a leading edge of a set pulse. The pulse generation circuit comprises an output stage gate having a first output transistor for having the output pulse to be activated level and a second output transistor for having the output pulse to be deactivated level; a first inverter array, for propagating the set pulse and driving the first output transistor; a second inverter array, for propagating a reset pulse, and for driving the second output transistor. To prevent the trailing edge of the set pulse from being delayed, the pulse generation circuit comprises a reset transistor disposed at an inverter output in the first inverter array, being driven in response to the reset pulse propagating through the second inverter array.
|
