发明名称 |
A METHOD FOR TESTING AN ELECTRONIC CIRCUIT BY LOGICALLY COMBINING CLOCK SIGNALS, AND AN ELECTRONIC CIRCUIT PROVIDED WITH FACILITIES FOR SUCH TESTING |
摘要 |
An electronic circuit has a plurality of nodes at which a plurality of clock signals are present in operational use. The clock signals should have a pre-determined timing relationship amongst themselves. The circuit includes logic circuitry having inputs connected to the nodes and having an output to provide a pulse train. Any discrepancy between the actual and ideal pulse trains indicates a fault. |
申请公布号 |
EP0780037(B1) |
申请公布日期 |
2003.12.17 |
申请号 |
EP19960917625 |
申请日期 |
1996.07.01 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
SACHDEV, MANOJ;ATZEMA, BOTJO |
分类号 |
G01R31/316;G01R31/28;G01R31/30;H03K19/00;(IPC1-7):H03K19/00 |
主分类号 |
G01R31/316 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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