发明名称 |
Semiconductor memory device having a hierarchial I/O strucuture |
摘要 |
Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.
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申请公布号 |
US6665203(B2) |
申请公布日期 |
2003.12.16 |
申请号 |
US20010866623 |
申请日期 |
2001.05.30 |
申请人 |
HITACHI, LTD.;HITACHI ULSI SYSTEMS CO., LTD. |
发明人 |
FUJISAWA HIROKI;KUBOUCHI SHUICHI;NINOMIYA KOICHIRO |
分类号 |
G11C11/409;G11C5/02;G11C5/06;G11C7/10;G11C8/02;G11C8/12;G11C8/14;G11C11/401;G11C11/407;G11C11/4093;H01L21/8242;H01L27/108;(IPC1-7):G11C5/02 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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