发明名称 Frequency doubler circuit arrangement
摘要 A frequency doubler circuit arrangement comprises a full wave rectifier circuit having an input and a first terminal, the first terminal being connected to a first supply terminal via a first current source, and the input forming an input of the frequency doubler circuit arrangement. A biased transistor circuit is also provided, having a first terminal connected to the first supply terminal via a second current source and being connected to the first terminal of the rectifier circuit. Output terminals of the rectifier circuit and the biased transistor circuit form differential output terminals of the frequency doubler circuit arrangement. The respective outputs of the rectifier circuit and the biased transistor circuit may be connected to a second supply terminal via either an active filter load or a passive filter load, such as an inductance-capacitance-resistance filter. Such a frequency doubler circuit may be employed in a radiotelephone device such that a single voltage controlled oscillator may be utilized to provide signal sources at more than one operating frequency.
申请公布号 US6664824(B2) 申请公布日期 2003.12.16
申请号 US20020202477 申请日期 2002.07.24
申请人 ZARLINK SEMICONDUCTOR LIMITED 发明人 LAWS PETER GRAHAM
分类号 H03B19/14;(IPC1-7):H03B19/00 主分类号 H03B19/14
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