发明名称 |
Method of fabricating a high voltage semiconductor device using SIPOS |
摘要 |
A high voltage semiconductor device including a semiconductor substrate on which a semi-insulating polycrystalline silicon layer is formed to alleviate electric field concentration in a field region, is disclosed. A thermal oxide layer is formed on the semi-insulating polycrystalline silicon layer to serve as a protective layer. The thermal oxide layer forms a good interface with the semi-insulating polycrystalline silicon layer compared to a wet etched oxide layer or a chemical vapor deposition (CVD) oxide layer, thereby decreasing the amount of leakage current. In addition, compared to a dual semi-insulating polycrystalline silicon layer, the thermal oxide layer exhibits a high surface protection effect and a high resistance against dielectric breakdown. It also allows a great reduction in fabrication time. In particular, the semi-insulating polycrystalline silicon layer is removed from the active region, thereby preventing the direct current (DC) gain of a device from being lowered within a low collector current range caused by the semi-insulating polycrystalline silicon layer.
|
申请公布号 |
US6660570(B2) |
申请公布日期 |
2003.12.09 |
申请号 |
US20020140181 |
申请日期 |
2002.05.08 |
申请人 |
FAIRCHILD KOREA SEMICONDUCTOR, LTD. |
发明人 |
KIM JIN-KYEONG;KIM JONG-MIN;KIM KYUNG-WOOK;KIM TAE-HOON;CHOI CHEOL;KIM CHANG-WOOK |
分类号 |
H01L29/73;H01L21/316;H01L21/329;H01L21/331;H01L29/06;H01L29/40;H01L29/732;H01L29/861;(IPC1-7):H01L21/332 |
主分类号 |
H01L29/73 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|