发明名称 Shared peripheral architecture
摘要 A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to the shared bus in response to an owner signal. A set of peripheral-share registers where a first member of the set includes an entry associated with each of the plurality of peripheral units and holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.
申请公布号 US6662253(B1) 申请公布日期 2003.12.09
申请号 US20000660577 申请日期 2000.09.13
申请人 STMICROELECTRONICS, INC. 发明人 GARY SONYA;TYGER KAREN
分类号 G06F13/362;G06F3/06;(IPC1-7):G06F13/38;G06F3/00 主分类号 G06F13/362
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