发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL circuit capable of realizing application of an accurate phase offset by providing an offset current application section into a charge pump circuit. SOLUTION: In the PLL circuit provided with: a voltage-controlled oscillator (40) the frequency of the output clock of which is controlled by an input voltage; a frequency divider (50) for dividing an output signal of the voltage-controlled oscillator; a phase comparator (10) for comparing a phase of an output signal of the frequency divider with a phase of a reference signal; a charge pump circuit (20a) driven by an output signal of the phase comparator; and a loop filter (30) for integrating an output of the charge pump circuit, and controlling the frequency of the voltage-controlled oscillator with a voltage stored in the loop filter, the charge pump circuit is provided with a means for generating an offset current to change the phase of the output clock. COPYRIGHT: (C)2004,JPO
申请公布号 JP2003347935(A) 申请公布日期 2003.12.05
申请号 JP20020148974 申请日期 2002.05.23
申请人 YOKOGAWA ELECTRIC CORP 发明人 SUGIHARA YOSHINOBU;HORIUCHI HITOSHI
分类号 H03L7/093;(IPC1-7):H03L7/093 主分类号 H03L7/093
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