发明名称 DUAL-MEMORY SYSTEM
摘要 PROBLEM TO BE SOLVED: To make a computer highly reliable and to facilitate error remediation and repair replacement in system operation. SOLUTION: A processor 1 and a system bus controller 3 are connected through a CPU bus and the system bus controller 3 and a memory device 4 are doubled and connected by a couple of system buses 13, and error detecting circuits 6, 80 and 85 which detect errors of respective buses, comparing circuits 51, 104 and 105 which compare output contents of the buses, bus switching circuits 7, 82 and 83, and mode setting circuits 100, 101 and 102 are provided in the system bus controller 3 and memory device 4. Outputs of error detecting circuits are exchanged between a couple of devices and the bus switching circuits are controlled according to the detection result of the error detecting circuit and setting contents of the mode setting circuits from the opposite side. COPYRIGHT: (C)2004,JPO
申请公布号 JP2003345676(A) 申请公布日期 2003.12.05
申请号 JP20030126675 申请日期 2003.05.01
申请人 MITSUBISHI ELECTRIC CORP 发明人 TANABE TAKASHI
分类号 G06F12/14;G06F11/18;G06F12/16;G06F13/00;(IPC1-7):G06F13/00 主分类号 G06F12/14
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