| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a test time of a semiconductor device with a flash ROM mounted thereon. <P>SOLUTION: When receiving a memory test pattern for a pattern input period, the flash ROM 40 latches the memory test pattern in its inside, and the latched data of memory test pattern are written in a memory cell array for a nonvolatile program period after a lapse of the pattern input period. The nonvolatile program period is a wait time irrelative of the input of the memory test pattern to the flash ROM 40. The entire test time for the semiconductor device 20 is reduced by utilizing the nonvolatile program period and entering the logic test pattern to test a logic circuit 30 such as a CPU within this period. <P>COPYRIGHT: (C)2004,JPO |
