FOLDED BIT LINE DRAM WITH VERTICAL ULTRA THIN BODY TRANSISTORS

摘要

A folded bit line DRAM device made of an array of memory cells is provided wherein each memory cell has a pillar which extends outwardly from a semiconductor substrate. Each pillar has a single crystalline first contact layer (304) and a single crystalline second contact layer (306) which are separated by an oxide layer (308). A single crystalline vertical transistor has an ultra thin single crystalline vertical first source/drain region (314) coupled to the first contact layer (304), an ultra thin single crystalline vertical second source/drain region (316) coupled to the second contact layer (306), and an ultra thin single crystalline vertical body region (312) which opposes the oxide layer (308) and couples the first (314) and the second (316) source/drain regions.