MEMORY ARRAY HAVING 2T MEMORY CELLS

摘要

The present invention relates to a memory array having a plurality of memory cells. In order to combine the compactness of DRAM with the speed and uncomplicated processing profits of SRAM the present invention proposes a memory array having a plurality of memory cells each comprising:- a storage transistor having a drain coupled to a word-line of said array, a source coupled to a bit-line of said array and a gate, and - a control transistor having a drain coupled to the gate of said storage transistor, a source coupled to said bit-line and a gate coupled to said word-line.