发明名称 |
Compute node to mesh interface for highly scalable parallel processing system |
摘要 |
An interface circuit for interfacing one or more compute nodes to a mesh is capable of serving a wide range of MPP systems. The interface circuit includes a first bus interface for interfacing with a first bus, a second bus interface for interfacing with a second bus, and a mesh interface. Control logic is coupled to the first bus interface, the second bus interface and the mesh interface. The control logic includes circuitry for placing the interface circuit in a first mode in which a computc node resides on the first bus and a second mode in which the compute node resides on the second bus. The first bus may be a split-envelope bus such as the MIPS Avalanche bus. The second bus may be a single-envelope bus such as the PCI bus. <IMAGE>
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申请公布号 |
EP1367499(A1) |
申请公布日期 |
2003.12.03 |
申请号 |
EP20020011858 |
申请日期 |
2002.05.28 |
申请人 |
FUJITSU SIEMENS COMPUTERS, LLC |
发明人 |
MYERS, MARK S. |
分类号 |
G06F15/173;(IPC1-7):G06F15/173 |
主分类号 |
G06F15/173 |
代理机构 |
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