发明名称 Chip scale package in which layout of wiring lines is improved
摘要 A semiconductor device of the present invention includes: a semiconductor chip having an electrode at a periphery thereof, a wiring board having a first surface and a second surface, the first surface of the wiring board being attached to the semiconductor chip, the board having an opening to expose the electrode of said semiconductor chip, and an external terminal arranged on the second surface of the wiring board and arranged inside of the wiring board compared with the opening. The semiconductor device has a wiring line laid on the second surface of the wiring board to electrically connect the electrode and the external terminal. The wiring line extends outside of said wiring board from the external terminal and detours said opening to reach the electrode.
申请公布号 US6657293(B1) 申请公布日期 2003.12.02
申请号 US20000679805 申请日期 2000.10.05
申请人 NEC CORPORATION;NEC ELECTRONICS CORPORATION 发明人 FUMIHIRA RYUUJIN
分类号 H01L23/12;H01L21/60;H01L21/82;H01L23/498;H01L23/528;(IPC1-7):H01L23/04;H01L23/48;H01L23/52 主分类号 H01L23/12
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