| 发明名称 |
Pad and via placement design for land side capacitors |
| 摘要 |
An integrated circuit package and land side capacitor with reduced power delivery loop inductance. The capacitor pads have vias that lie underneath the land side capacitor, and have interposed digits. |
| 申请公布号 |
US6657275(B1) |
申请公布日期 |
2003.12.02 |
| 申请号 |
US19990366439 |
申请日期 |
1999.08.02 |
| 申请人 |
INTEL CORPORATION |
发明人 |
CHUNG CHEE-YEE;FIGUEROA DAVID G.;LI YUAN-LIANG |
| 分类号 |
H01L23/522;H01L23/528;H05K1/02;H05K1/11;(IPC1-7):H01L29/00 |
主分类号 |
H01L23/522 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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