| 摘要 |
A software program to translate a Verilog UDP (User Defined Primitive) into basic logic gates, in order to allow easier porting into other HDL languages and non-Verilog models, such as the LogicVision model. In a preferred embodiment the program is in Perl script, and reads in a Verilog source file. On finding a UDP, the script writes out a gate level description of the UDP into a Perl hash data structure, which is later used to output a LogicVision model.
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