| 摘要 |
A data processing system comprises a plurality of I/O channels, a plurality of memories and data routing means between the I/O channels and the memories. The data routing means includes first bus means for enabling selectively routing of the data to and from the memories, second bus means for enabling routing the data to and from the I/O channels, and a further plurality of data processors operative to couple the first bus means and the second bus means. This architecture allows for flexible processor allocation and memory sharing in a parallel processing system.
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