| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a zigzag address generating apparatus contributing a reduction in memory capacity by decreasing the number of conversion ROMs for generating zigzag addresses. <P>SOLUTION: The zigzag address generating apparatus is provided with: a counter 10 for making count operations; an address conversion memory 20h for storing address data to read pixel data from a pixel storage memory 30 by using an output of the counter 10 in the horizontal alternate order; and a selection circuit 40 for outputting an output of the address conversion memory 20h as it is to the pixel storage memory 30 as a read-out address signal when the horizontal alternate order is selected or for outputting an output of the address conversion memory 20h while replacing high-order bits of the output of the address conversion memory 20h with the low-order bits thereof to the pixel storage memory 30 as a read-out address signal when the vertical alternate order is selected. <P>COPYRIGHT: (C)2004,JPO</p> |
