发明名称 PLL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a PLL circuit which shortens the lockup time and enhances the S/N ratio. <P>SOLUTION: After start of lockup action, switching means 25 and 26 are switched during the switching time by means of a switching control means 3; and based on the phase difference from a phase comparator 1, currents of different current values flow to a voltage controlled oscillator 5 via a low-pass filter 4, so the voltage controlled oscillator 5 can output the input signal of target frequency at a high speed, thus the PLL circuit can shorten the lockup time. <P>COPYRIGHT: (C)2004,JPO
申请公布号 JP2003338753(A) 申请公布日期 2003.11.28
申请号 JP20020145303 申请日期 2002.05.20
申请人 FUJITSU LTD 发明人 YAGASHIRA SHOICHI;BABA HIROSHI
分类号 H03L7/093;H03L7/089;H03L7/107;H03L7/18 主分类号 H03L7/093
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