CONFIGURABLE DATA PROCESSOR WITH MULTI-LENGTH INSTRUCTION SET ARCHITECTURE

摘要

Digital processor apparatus (1904) having an instruction set architecture (ISA) with instruction words of varying length. In the exemplary embodiment, the processor comprises an extended user-configurable RISC processor with four-stage pipeline (fetch, decode, execute, and writeback) and associated logic (1902, 1908 and 1906) that is adapted to decode and process both 32-bit and 16-bit instruction words present in a single program, thereby increasing the flexibility of the instruction set, and allowing for greater code compression and reduced memory overhead. Free-form use of the different length instructions is provided with no required mode shift. An improved instruction aligner (1908) and code compression architecture is also disclosed.