发明名称 |
Circuit to manage and lower clock inaccuracies of integrated circuits |
摘要 |
A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.
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申请公布号 |
US2003221143(A1) |
申请公布日期 |
2003.11.27 |
申请号 |
US20020154754 |
申请日期 |
2002.05.23 |
申请人 |
KURD NASSER A.;BARKATULLAH JAVED S.;DIKE CHARLES |
发明人 |
KURD NASSER A.;BARKATULLAH JAVED S.;DIKE CHARLES |
分类号 |
G06F1/10;G06K7/00;H03L7/081;H03L7/089;(IPC1-7):G11B5/00;G06K5/04;G11B20/20 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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