| 摘要 |
1315340 Error detection and correction INTERNATIONAL BUSINESS MACHINES CORP 13 Nov 1970 [24 Dec 1969] 54023/70 Heading G4A In data processing apparatus, errors in data words each including k check bits are detected and/or corrected using k syndrome signals each produced by a respective logic circuit, each check bit being provided to precisely one of the logic circuits, and each data bit to three or a larger odd number of the logic circuits, with substantially equal numbers of data and check bits being provided to each logic circuit. Each logic circuit is an EXCL-OR tree providing a syndrome bit. The syndrome bits produce an "error" signal via an OR gate, and also go to an EXCL-OR gate, the "error"signal being ANDed with the output of the EXCL-OR gate to indicate "single error" and with its inverse to indicate "double error". The syndrome bits and their inverses are combined in AND gates enabled by the "single error" signal to locate the single error (if present) this being corrected using a respective EXCL-OR gate of a row of such gates to which the word is fed in parallel. Each "logic circuit" receives a respective 8-bit byte of the 64 information bits in the word (this choice permits the same hardware to be used for byte parity checking elsewhere in the system), others of the information bits, and a respective one of the 8 check bits provided in the word. The check bits were generated from the information bits for inclusion in the word by EXCL-OR trees similar to the "logic circuits" (less the check bit inputs). |
