发明名称 MPEG Decoder with a shared memory
摘要 <p>The circuit monitors the delay time of the decoder in order to determine whether it needs priority access to the memory. The circuit (16) comprises a microprocessor (6) and an MPEG decoder (4) for decoding a series of images, with a memory (12) being common to both the microprocessor and the memory. There is also a circuit (18) for evaluation of the delay of the decoder. If the delay of the decoder is greater than a predetermined value, then a control circuit (14) gives the decoder priority of access to the memory, but if this is not the case, then the control circuit gives the microprocessor priority of access to the memory. A clock circuit is used, and the activity of the delay circuit during a fixed number of clock cycles is monitored in order to determine conditions which establish which unit should have priority.</p>
申请公布号 EP1098525(A3) 申请公布日期 2003.11.26
申请号 EP20000410136 申请日期 2000.11.02
申请人 STMICROELECTRONICS S.A. 发明人 MOUTIN, JEAN-MICHEL;MARTY, PIERRE
分类号 G06F12/00;G06T9/00;H04N7/26;H04N7/50;(IPC1-7):H04N7/50 主分类号 G06F12/00
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