发明名称 |
Semiconductor device capable of internally adjusting delayed amount of a clock signal |
摘要 |
A plurality of internal circuits each include a respective clock adjusting circuit that adjusts the phase of a clock signal given by a clock buffer. Even if a difference in delayed amount of the clock signal is generated by drawing clock interconnections, a different adjustment can be made for each internal circuit, whereby the operation of synchronized circuits respectively included in the plurality of internal circuits can be improved.
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申请公布号 |
US6653877(B2) |
申请公布日期 |
2003.11.25 |
申请号 |
US20000741803 |
申请日期 |
2000.12.22 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
TSUJINO MITSUNORI |
分类号 |
G11C11/413;G06F1/10;G11C7/22;G11C11/401;G11C11/407;G11C11/41;H01L21/82;H01L21/822;H01L27/04;H03K5/14;(IPC1-7):H03H11/26 |
主分类号 |
G11C11/413 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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