| 摘要 |
A clock and data recovery circuit includes a phase-shift circuit having a switch, which receives multiphase clocks, for selecting and outputting a plurality of clock pairs from among the multiphase clocks, and a plurality of interpolators, which receive the plurality of clock pairs output from the switch, for outputting clock signals in which delay time is stipulated by time obtained by performing interior division of the phase difference between the clocks of the pair; a plurality of latch circuits which receive input data in common; a phase detecting circuit for detecting and outputting phase, with respect to the clock, of a transition point of the input data from the outputs of the plurality of latch circuits; a filter for smoothing the output of the phase detecting circuit; and a control circuit for controlling clock phase by outputting control signals for controlling the interpolators and/or switch of the phase-shift circuit based upon the filter output. The plurality of interpolators are divided into a plurality of groups in relation to the control signals supplied from the control circuit, interpolators in the same group are supplied with the same control signal from the control circuit, and interpolators in different groups are supplied separately with the control signals from the control circuit.
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