发明名称 |
Digital multi-phase clock generator |
摘要 |
A digital multi-phase clock generator includes a reference clock input and first and second digitally-programmable delay lines. The first and second delay lines are coupled in parallel with one another, in series with the reference clock input. Each delay line includes a delay control input. The first delay line has a plurality of phase outputs which are synchronized with the reference clock input and have different phases from one another. The generator further includes a phase detector and a delay control circuit, which are coupled with second delay line to form a phase-locked loop. The delay control circuit has a digital delay control output, which is coupled to the delay control inputs of both the first and second delay lines. The phase-locked loop adjusts delay through the first and second delay lines to lock a phase of an output of the second delay line to a phase of the reference clock input.
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申请公布号 |
US2003215039(A1) |
申请公布日期 |
2003.11.20 |
申请号 |
US20020146634 |
申请日期 |
2002.05.14 |
申请人 |
BLOCK STEFAN G.;REUVENI DAVID R. |
发明人 |
BLOCK STEFAN G.;REUVENI DAVID R. |
分类号 |
H03K5/156;H03L7/081;H03L7/089;(IPC1-7):H03D3/24 |
主分类号 |
H03K5/156 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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