发明名称 Automatic design of VLIW processors
摘要 A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.
申请公布号 US6651222(B2) 申请公布日期 2003.11.18
申请号 US20020068216 申请日期 2002.02.06
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 GUPTA SHAIL ADITYA;RAU B. RAMAKRISHNA;KATHAIL VINOD K.;SCHLANSKER MICHAEL S.
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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