发明名称 |
Architecture for performing fast fourier-type transforms |
摘要 |
A processor for performing fast Fourier-type transform operations is disclosed. At least one multiplier and a plurality of adders are provided to perform butterfly operations comprising three multiply operations and a plurality of add operations. Internal wordlengths are wider than wordlengths of input values to reduce rounding error.
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申请公布号 |
US2003212722(A1) |
申请公布日期 |
2003.11.13 |
申请号 |
US20020211651 |
申请日期 |
2002.08.02 |
申请人 |
INFINEON TECHNOLOGIES AKTIENGESELLSCHAFT. |
发明人 |
JAIN RAJ KUMAR;LOW SEO HOW |
分类号 |
G06F17/14;(IPC1-7):G06F15/00 |
主分类号 |
G06F17/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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