发明名称 Packet buffer memory with integrated allocation/de-allocation circuit
摘要 A buffer memory with a memory allocation and de-allocation circuit. The buffer memory has an address space divided into address blocks and a memory address space divided into memory blocks. The circuit, in response to an allocation request for an allocation of a certain size buffer, allocates sufficient address blocks and memory blocks for the buffer. The circuit, in response to a de-allocation request to de-allocate a certain size of memory, de-allocates whole unused address blocks and memory blocks.
申请公布号 US2003212875(A1) 申请公布日期 2003.11.13
申请号 US20030410379 申请日期 2003.04.09
申请人 GRESHAM PAUL 发明人 GRESHAM PAUL
分类号 G06F12/02;H04L12/56;(IPC1-7):G06F12/00 主分类号 G06F12/02
代理机构 代理人
主权项
地址