| 摘要 |
A phase-frequency detector (PFD) with increased phase error gain during acquisition of phase lock when used in a phase-locked loop (PLL). The reference and feedback signals are time-multiplexed into N pairs of input signals. Each pair of input signals is detected by one of N phase-frequency detectors, which produce N pairs of detection signals indicative of phase differences between the reference and feedback signals. These N pairs of detection signals are combined in separate logical-OR operations to produce a frequency increase control signal and a frequency decrease control signal indicative of when the feedback signal frequency is lower and higher, respectively, than the reference signal frequency. These control signals have respective substantially nonzero signal values that vary in respective relations to the difference between the reference and feedback signal phases when such phase difference is less than 2pi radians, and repeat with patterns having phase difference intervals of 2Npi radians when such phase difference is greater than 2pi radians.
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