| 摘要 |
PROBLEM TO BE SOLVED: To prevent destruction of a result in which write is performed by normal operation, even in a state of the half way at which an operation mode being different from a normal operation mode is started. SOLUTION: A control signal generating circuit 150 performs control for a memory cell array 200 in a non-normal operation mode being different from a normal operation mode in which write of data to the memory cell array 200 and read of data from the memory cell array 200 are performed. The control signal generating circuit 150 starts a test mode responding to entry sequence of a test mode based on an indication signal, performs operation of a set and corresponding test mode after setting the test mode responding to set sequence of a test mode based on the other indication signal, after that, controls so that a test mode is released by test mode release processing based on other indication signal, and activation processing for the memory cell array 200 is prohibited in a period in which a test mode is set. COPYRIGHT: (C)2004,JPO |
