发明名称 MULTILAYER WIRING BOARD AND ITS MANUFACTURING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a method for plating to filler via with high reliability by which hole filling can be completed in a short time in a plating step for filling a micro-diameter via hole connecting upper and lower conductor wiring layers when manufacturing a multilayer wiring board of a multilayer structure wherein an insulation layer made of an organic insulation material such as a polyimide resin and a wiring layer made of a conductor material such as cupper are alternately stuck. SOLUTION: Plating is conducted by changing the current density at at least two steps in an electrolytic plating step. The current density for electrolytic plating is made smallest in the initial stage, and it is gradually increased thereafter. The multilayer wiring board can be used as an interposer for mounting an semiconductor element. COPYRIGHT: (C)2004,JPO
申请公布号 JP2003318544(A) 申请公布日期 2003.11.07
申请号 JP20020118932 申请日期 2002.04.22
申请人 TOPPAN PRINTING CO LTD 发明人 ONO NAOTO
分类号 H05K3/42;H01L23/12;H05K3/46;(IPC1-7):H05K3/46 主分类号 H05K3/42
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