Verfahren und Gerät zum automatischen Entwurf logischer Schaltung und Multiplikator,申请号DE19936032817T-传众专利搜索

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发明名称	Verfahren und Gerät zum automatischen Entwurf logischer Schaltung und Multiplikator
摘要
申请公布号	DE69332817(T2)	申请公布日期	2003.11.06
申请号	DE19936032817T	申请日期	1993.12.28
申请人	MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.	发明人	TSUBATA, SHINTARO;NISHIYAMA, TAMOTSU
分类号	G06F7/53;G06F7/52;G06F17/50;(IPC1-7):G06F17/50	主分类号	G06F7/53
代理机构		代理人
主权项
地址

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