发明名称 |
Clock generating circuit and method |
摘要 |
A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.
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申请公布号 |
US2003206067(A1) |
申请公布日期 |
2003.11.06 |
申请号 |
US20020136390 |
申请日期 |
2002.05.02 |
申请人 |
WONG KENG L.;BINDAL NIRAJ;MA HONG-PIAO;GEANNOPOULOS GEORGE;TAYLOR GREG F.;BURTON EDWARD A. |
发明人 |
WONG KENG L.;BINDAL NIRAJ;MA HONG-PIAO;GEANNOPOULOS GEORGE;TAYLOR GREG F.;BURTON EDWARD A. |
分类号 |
G06F1/10;H03K3/03;H03K5/13;H03K5/15;(IPC1-7):H03B1/00 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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