| 摘要 |
An NROM memory device, wherein the memory cells (1) are provided with charge storage regions (12) of insulating material, such as silicon nitride. The memory device includes a row decoder (50) comprising a plurality of drivers (53); during programming, a first driver supplies a first voltage (Vpp) having a first value to a selected wordline (WL), while the other drivers (53) are configured so as to supply a second voltage (Voff) having a second non-zero value, lower than the first value, to the other wordlines. Thereby, the gate-drain voltage drop of the deselected cells is reduced, and thus spurious erasing of the deselected cells connected to the selected bitline is reduced. Consequently, the reliability of the memory device is improved considerably and the life thereof is lengthened, thanks to the reduction in the charge injected into the charge storage region (12). <IMAGE> <IMAGE>
|
