发明名称 Method of manufacturing a dual gate semiconductor device with a poly-metal electrode
摘要 In order to realize a dual gate CMOS semiconductor device with little leakage of boron that makes it possible to divisionally doping a p-type impurity and an n-type impurity into a polycrystalline silicon layer with one mask, a gate electrode has a high melting point metal/metallic nitride barrier/polycrystalline silicon structure. The boron is pre-doped in the polycrystalline silicon layer. The phosphorus or arsenic is doped in an n-channel area. Then, the annealing in a hydrogen atmosphere with vapor added therein is performed. As a result, the boron is segregated on the interface of the metallic nitride film and the phosphorus is segregated on the interface of the gate oxide film, for forming an n+ gate.
申请公布号 US2003203611(A1) 申请公布日期 2003.10.30
申请号 US20030448351 申请日期 2003.05.30
申请人 YAMAMOTO NAOKI 发明人 YAMAMOTO NAOKI
分类号 H01L27/092;H01L21/28;H01L21/8238;(IPC1-7):H01L21/823;H01L21/320;H01L21/476 主分类号 H01L27/092
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