发明名称 |
Bi-directional serializer/deserializer with discretionary loop-back |
摘要 |
A serializer/deserializer pair with a discretionary loop-back mechanism is disclosed that enables a redundant high-bandwidth node architecture that benefits from the clever re-use of two identical integrated circuits. The first is an add/drop multiplexor and the second comprises the serializer/deserializer pair with discretionary loop-back. The illustrative embodiment comprises: a first serializer that serializes a first series of r-bit words to generate a first series of s-bit words; a first deserializer that deserializes a second series of s-bit words to generate a second series of r-bit words; and a multiplexor for selecting a third series of r-bit words from the first series of r-bit words and the second series of r-bit words; wherein r and s are both positive integers and r>=s.
|
申请公布号 |
US2003202544(A1) |
申请公布日期 |
2003.10.30 |
申请号 |
US20020112551 |
申请日期 |
2002.03.29 |
申请人 |
BARNES DAVID ANDREW;PITIO WALTER MICHAEL |
发明人 |
BARNES DAVID ANDREW;PITIO WALTER MICHAEL |
分类号 |
H04J3/08;(IPC1-7):H04J3/04 |
主分类号 |
H04J3/08 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|