Input staging logic for latching source synchronous data

摘要

A circuit arrangement, program product and method in one aspect utilize three stage input staging logic to receive source synchronous data in a source synchronous communications system such as a PCI-compatible communication system. In another aspect, two stage input staging logic is supplemented by at least one holding latch disposed intermediate the output of the two stage input staging logic and a common clock synchronizing circuit to effectively increase the hold time of a staging latch in one of the latching stages prior to common clock synchronization. The holding latch may be clocked concurrently with at least one other staging latch in the input staging logic that is clocked later in a data phase than the staging latch that feeds the holding latch so that the data clocked into both such staging latches is available for common clock synchronization at roughly the same point in time.